The present invention relates to a novel lead frame and a semiconductor device in which a semiconductor chip is bonded to the lead frame and, more particularly, to a structure of an external ring for enhancing the strength of sealing resin for the same.
There is a semiconductor package as shown in FIG. 1 which can be mounted on a printed wiring board or the like through an organic substrate having external connection terminals such as solder balls or the like.
Referring to FIG. 1, a semiconductor chip 51 is mounted on a surface of a multilayer organic wiring board 50 having two to six layers or so made of an organic material. The electrode pads of the semiconductor chip 51 and a wiring film 52 formed on a surface of the multilayer organic wiring board 50 are connected to each other by means of wire bonding utilizing gold wires 53.
On the rear surface of the multilayer organic wiring board 50, there are provided solder balls (external connection terminals) 55 which are electrically connected to the wiring film 52 on the front surface via through holes 54. The solder balls 55 are exposed to the outside through openings formed through a solder resist film 56. The semiconductor chip 51 together with the gold wires 53 is sealed by a sealing resin 57.
In a semiconductor package 58 having the above-described configuration, the solder balls 55 formed on the rear surface are connected to a printed wiring board 59. The multilayer organic wiring board 50 is frequently referred to as xe2x80x9cball grid array (BGA)xe2x80x9d because a multiplicity of solder balls 55 are arranged in the form of a grid. Therefore, the semiconductor package 58 having such a multilayer organic circuit board 50 is referred to as a xe2x80x9cBGA packagexe2x80x9d.
In the semiconductor package 58 as described above, reduction of a wiring pitch has been limited by the fact that the electrode pads of the semiconductor chip 51 and the wiring film 52 of the multilayer organic wiring board 50 have been connected by means of wire bonding. Efforts toward an increased number of pins have been also limited in other semiconductor packages such as TCPs (tape carrier packages) because the leads have been formed by etching a copper foil bonded to an insulating film base and this has resulted in limitations such as a reduction in the width of the leads due to side etching.
Under such circumstances, the assignee of the present invention has already proposed a semiconductor package having a super-many pin structure obtained by bonding a novel lead frame and a semiconductor chip.
FIG. 2 shows an example of the semiconductor package having the super-many pin structure.
In this semiconductor package 78, a plurality of electrode pads 76 are formed along the periphery of a front surface of a semiconductor chip 75 (a lower surface of the semiconductor chip 75 in FIG. 2). At the central portion of the surface of the semiconductor chip 75 excluding the region where the electrode pads 76 are formed, there is located a wiring film 68 with an adhesive layer 74 constituted by an adhesive sheet or the like interposed therebetween. The wiring film 68 is configured by laminating an insulation film 67 on a lead pattern 65. The adhesive layer 74 not only bonds the semiconductor chip 75 and the wiring film 68 but also serves as a buffering material for protecting an element formation region of the semiconductor chip 75 inside the region where the pads are formed.
External connection terminals 70 constituted by solder balls are formed so as to protrude above the wiring film 68 at ends of the lead patterns 65. A plurality of leads 69 are extend from the wiring film 68 in correspondence with the lead pattern 65, and the extended ends of the leads 69 are connected to the electrode pads 76 of the semiconductor chip 75 through bumps 72. An external ring 71 is provided outside the semiconductor chip 75 so as to surround the same. Sealing resin 77 is filled in the gap between the semiconductor chip 75 and the external ring 71.
A lead frame is formed by the external connection terminals 70, the insulation film 67, the lead patterns 65 for the circuit wiring, leads the 69 and the external ring 71.
Due to the above-described structure, the semiconductor chip 75 and the lead patterns 65 are bonded to each other with high accuracy, and the external size of the semiconductor package 78 is made as close to the size of the semiconductor chip 75 as possible by forming the balls 70 for the external terminals on the upper surface of the semiconductor chip 75.
A brief description will now be made on processes for fabricating the semiconductor package 78.
First, as shown in FIG. 3A, a metal base 61 having a three-layer structure is prepared for the fabrication of the lead frame. The metal base 61 is obtained by forming an aluminum film 63 on a surface of a substrate 62 made of copper or a copper alloy (hereinafter referred to xe2x80x9ccopper substratexe2x80x9d) and forming a nickel film 64 on the aluminum film 63.
Next, as shown in FIG. 3B, a plurality of lead patters 65 are formed on a surface of the metal base 61 by means of electrolytic plating of copper.
Then, as shown in FIG. 3C, slits 66 are formed to define an external configuration of the lead frame for each chip.
Next, as shown in FIG. 3D, the insulation film 67 is laminated on the lead patterns 65 to form the wiring film 68 constituted by the lead patterns 65 and the insulation film 67. The plurality of leads 69 extend from the wiring film 68 in correspondence with the lead patterns 65.
Next, as shown in FIG. 3E, electrolytic plating is performed to form the external connection terminals (solder balls) 70 on the lead patterns 65 coated with the insulation film 67.
Next, as shown in FIGS. 3F and 3G, the copper substrate 62, the aluminum film 63 and the nickel film 64 on the metal base 61 are successively removed by means of selective etching so as to leave the external ring 71, thereby separating the lead patterns 65 (including the leads 69) individually from one another.
Next, as shown in FIG. 3H, the bump 72 is formed on the end of each of the leads 69 extending from the wiring films 67.
Up to this process, a lead frame 73 before assembling the semiconductor chip is completed.
Then, the process proceeds to the fabrication of a semiconductor package wherein the semiconductor chip 75 is assembled into the lead frame 73.
First, as shown in FIG. 3I, the semiconductor chip 75 is positioned and fixed on the rear surface side of the wiring film 68 with the adhesive layer 74 interposed therebetween.
Next, as shown in FIG. 3J, the tip end of each lead 69 is connected to the electrode pad 76 of the semiconductor chip 75 through the bump 72.
Next, as shown in FIG. 3K, the liquid sealing resin 77 is injected into the gap between the semiconductor chip 75 and the external ring 71 using a dispenser or the like and is set to integrate peripheral components.
Finally, as shown in FIG. 3L, any unnecessary part is cut off at the peripheral edge of the external ring 71.
This completes the semiconductor package 78 having a super-many pin structure shown in FIG. 2.
In the semiconductor package 78, a structure having super-many pins in the excess of that achievable up to now is realized by forming the lead patterns 65 on the metal base 61 by means of electrolytic plating of copper during the fabrication of the lead frame 73 and further by forming the external connection terminals (solder balls) 70 on the lead patterns 65 by means of electrolytic plating.
Further, the metal base 61 is subjected to selective etching to leave the external ring 71 which defines the external configuration of the package. As a result, the positional accuracy between the external configuration of the package and the external connection terminals 70 is assured to facilitate alignment during the mounting of the package. In addition, a so-called CSP (chip size package) structure is achieved wherein the size of the package is maintained at the same level as the chip size.
When the semiconductor package 78 is fabricated, the sealing resin 77 is filled in the gap between the semiconductor chip 75 and the external ring 71 by injecting the resin from the rear side of the semiconductor chip 75. This is because problems as described below arise if the resin is injected from the front side of the semiconductor chip 75.
(1) It is difficult to fill the gap between the semiconductor chip 75 and the external ring 71 with the sealing resin 77 by injecting the resin from the front side of the semiconductor chip 75 because the gap is narrow (on the order of 0.1 mm).
(2) The sealing resin 77 will stick even to the external connection terminals (solder balls) 70 if there is any error in the relative position of the semiconductor package 78 and the dispenser.
(3) The operation of injecting resin is difficult to perform because of the presence of the leads 69.
On the contrary, injection of the resin from the rear side of the semiconductor chip 75 allows the sealing resin 77 to be smoothly filled in the gap between the semiconductor chip 75 and external ring 71 because this resin injecting operation is not hindered by components such as the leads 69, the external connection terminals 70 or the like and a sufficient amount of sealing resin 77 will be supplied utilizing a step formed between the rear side of the semiconductor chip 75 and the external ring 71.
While the strength of the semiconductor package 78 having the above-described structure in the region between the semiconductor chip 75 and the external ring 71 has been maintained by injecting a sufficient amount of sealing resin 77 to the gap between the semiconductor chip 75 and external ring 71, in this case, sealing strength has been insufficient because it has depended only upon surface bonding strength between the external ring 71 and sealing resin 77.
In order to solve the above-described problem, according to the present invention, there are provided a semiconductor device and a lead frame which form a stable external ring structure wherein not only bonding strength between the external ring and the sealing resin but also mechanical strength is improved.
A semiconductor device according to the present invention comprises a semiconductor chip having a plurality of electrode pads formed at the periphery of a front surface thereof, a wiring film formed on the front surface side of the semiconductor chip by laminating an insulation film on lead patterns, external connection terminals formed so as to protrude above the same, a plurality of leads extending from the wiring film and connected to the electrode pads on the semiconductor chip at the tip ends of the extensions thereof, an external ring provided so as to surround the semiconductor chip and formed with a plurality of through holes or blind holes, and sealing resin filled in the gap between the semiconductor chip and the external ring.
With the configuration of the semiconductor device according to the invention as described above, since the external ring formed with the plurality of through holes or blind holes is provided to surround the semiconductor chip and the sealing resin is filled in the gap between the semiconductor chip and the external ring, bonding strength is enhanced as a result of an increase in the area of contact between the sealing resin and the external ring due to the presence of the holes on the external ring.
A lead frame according to the present invention comprises a wiring film formed by laminating an insulation film on lead patterns, external connection terminals formed so as to protrude above the wiring film, a plurality of leads extending from the wiring film and forming connecting portions to electrode pads on a semiconductor chip at the tip ends of the extensions thereof, and an external ring provided outside the wiring film, having an opening capable of housing the semiconductor chip and formed with a plurality of through holes or blind holes.
With the configuration of the lead frame according to the invention as described above, since there is provided the external ring having the opening capable of housing the semiconductor chip and formed with the plurality of through holes or blind holes, the external ring will contact with resin in an increased area during injection of the resin performed later for sealing as a result of an increase in the surface area of the external ring due to the presence of the holes thereon.